The present invention relates to crystal-stabilized integrated circuit oscillators and more particularly to phase alignment circuits for these oscillators.
Crystal-controlled oscillators use the high Q of an electromechanical resonator (a quartz crystal) to stabilize an oscillating circuit at a desired frequency. Such circuits can achieve a frequency stability in the parts-per-million range, and there is no other practical way to achieve such a constant frequency reference in an integrated circuit. Crystal-controlled oscillators are therefore extremely important, and likely to remain so.
Crystal-controlled oscillators pose some difficulties in design, and one of these is start-up. A variety of startup circuits have been proposed; see e.g. B. Parzen, DESIGN OF CRYSTAL AND OTHER HARMONIC OSCILLATORS (1983), at page 415; Unkrich et al., xe2x80x9cConditions for Start-Up in Crystal Oscillators,xe2x80x9d 17 IEEE J. Solid-State Circuits 87 (1982).
Other difficulties are present in the specific context of low-power CMOS oscillator implementations. Many portable applications are designed for low operating voltage and low power consumption, but also require the frequency stability of a crystal oscillator. To reduce power consumption, such low-power CMOS oscillator circuits are typically operated in the weak inversion regime (where gate voltages are only slightly greater than the threshold voltage). However, in the weak inversion regime the gain tends to be lower, and thus start-up is a particularly critical problem. See e.g. U.S. Pat. No. 5,546,055, which is hereby incorporated by reference.
Low-power crystal oscillators, such as those used in real-time clock circuits, put out a signal whose duty cycle depends upon a number of different factors, such as threshold voltage, supply voltage, crystal characteristics, parasitics, temperature, etc. A 50% duty cycle can be achieved by passing this signal through a divide-by-2 circuit, but this reduces the frequency to one half that of the crystal.
It is possible to achieve a 50% duty cycle at full frequency by doubling the crystal frequency and then dividing the doubled frequency by two. This solution is not economical; only a few frequencies of crystal are made in sufficient volume to obtain minimum price (e.g. 38.4 kHz, 32.768 kHz), so this option would be too expensive for common usage.
A 50% duty cycle is useful for many applications; particularly in switch-mode power converters. A 50% duty cycle is also desirable for digital circuitry which uses both clock edges.
The innovative circuit described below uses paired capacitors to take a square wave of constant period but indeterminate duty cycle and to transform it into a square wave of equal period and deterministic duty cycle, e.g. 50%. The preferred embodiment alternately charges and discharges two equal capacitors, and passes the resulting ramp voltages through a comparator to produce a square wave output with a 50% or other predetermined duty cycle.
The innovative circuit can also be controlled to produce virtually any desired duty cycle. The selectable duty cycle allows the innovative circuit to be used for special purpose devices, as well as for charge pumps, converters, specialty clocks, etc. Finally, the innovative circuit can be used as a clock multiplier.